1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods and structures for reducing charges induced by external factors, such as plasma processing.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using semiconductor-manufacturing tools, such as exposure tool or a stepper. As an example, an etch process may be performed on the semiconductor wafers to shape objects on the semiconductor wafer, such as polysilicon lines, each of which may function as a gate electrode for a transistor. As another example, a plurality of metal lines, e.g., aluminum or copper, may be formed that serve as conductive lines that connect one conductive region on the semiconductor wafer to another.
Various processes are performed on semiconductor substrates in manufacturing integrated circuit products. Some of these processes may be plasma based processing. For example, plasma processing in semiconductor manufacturing may include chemical vapor deposition (CVD), etching, dry cleaning (instead of wet chemical rinsing), etc. Plasma processing involves creating partially ionized gas by applying an electric filed. Ions can be accelerated, resulting ion bombardment of a wafer surface. This bombardment provides for plasma etching by direct means (sputtering, ion beam milling) or by indirect means by assisting chemical etching. Generally, positive ion-electron pairs are created by ionization reactions, however, accumulation of charges generally occur when using plasma processing. These charges may cause damage to circuits (e.g., transistors) formed on semiconductor wafers.
When integrated circuits are formed, tests are performed to determine the correctness in the operation of the circuits. For electrical testing of a discrete transistor (e.g., field effect transistor (FET)), the gate, source, and drain of the transistor are typically connected to probe pads. In order to reduce plasma processing induced damage of gate dielectric during the fabrication process or in the testing process, protection diodes are typically connected in parallel to the transistor.
Turning now to FIG. 1, a stylized depiction of a prior art integrated circuit device is illustrated. FIG. 1 illustrates a field-effect transistor (FET) that is formed on a substrate 105, e.g., a p-type silicon substrate. Various shallow trench isolation (STI) 107 regions are formed. In many cases the STI regions 107 are formed using oxide depositions on the substrate 105. A p+ doped region 109, as well as n+ doped regions 122 are formed are formed on the substrate 105. A polysilicon conductor (PC) 128 may be formed above a gate oxide region (GOX) 129 on the substrate 105 to form the gate region 126 of the FET. In some embodiments, the polysilicon conductor (PC) may be replaced with a metal conductor. That is, in some embodiments, PC may refer to the gate electrode, wherein in other embodiments, PC may refer to a metal conductor operating as a gate electrode. A contact region (CA) 110 may be formed above the doped n+ region for a source region 121. Similarly, another CA 110 may be formed above an n+ region for a drain region 131.
Further, a CA 110 may be formed above another n+ region and another CA 110 may be formed above the p+ doped region 109. Together, p+ region 109 and the n+ region provide for a PN junction for forming a diode region 116. A test substrate pad 115 may be connected to the contact 110, which may form a circuit connection to the anode terminal of the diode 116. A test pad 120 may be connected to the source 121, a test pad 125 may be connected to the gate 126, and a test pad 130 may be connected to the drain of the transistor. The circuit provided by the structure illustrated in FIG. 1 is depicted in FIG. 2.
FIG. 2 illustrates a stylized prior art circuit diagram of the structure provided by the structure of FIG. 1. As described above, the structure of FIG. 1 comprises a transistor that is connected to a diode formed to provide protection from plasma process charges, as described above. The structure of FIG. 1 comprises a gate 220 and protection diode 210 that is connected to the gate node 127, such that the diode 210 is connected in parallel to the gate 220. The protection diode 210 is used to reduce the plasma processing-induced charge damage of the gate dielectric during the fabrication process. One of the problems associated with the prior art solution using the protection diode includes diode leakage problems. When performing testing of the transistor, measuring gate leakage may become inaccurate due to the diode leakage. Further, any variations in the pitch of the formations during processing can lead to significant diode leakage using the state of the art process.
The present disclosure may address and/or at least reduce one or more of the problems identified above.